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MAS3690CD データシート(PDF) 18 Page - Dynex Semiconductor |
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MAS3690CD データシート(HTML) 18 Page - Dynex Semiconductor |
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18 / 41 page  MA3690/1/3 18/41 Symbol Description Min. Typ. Max. Units t40 RESETN ↓ to ADEN ↓ 80 nS t41 PUCN ↑ to RESETN ↑ 2t t42 RESETN ↑ to ADENN ↑ 2t 2t + 80 nS t43 Initialisation word set-up wrt RESETN ↑ 15 nS t44 Initialisation word HOLD wrt RESETN ↑ 20 nS t45 Minimum RESETN pulse width 90 nS t46 Minimum CK12 high 33 nS t47 Minimum CK12 low 20 nS t48 CK12 ↑ to CK4 ↑ 90 nS t49 CK12 ↓ to CK4 ↓ 90 nS t50 HALTREQN pulse width 1t t51 HALTREQN ↑ to HALTEDN ↑ 55 nS t52 HALTREQN ↑ to CODENN ↓ 1t 2t t53 CODENN ↑ to CODENN ↓ 2t t54 RT-RT minimum validation time 1) RT1 = 0 RT0 = 0 55.75 56.25 uS 2) RT1 = 0 RT0 = 1 61 75 62.25 uS 3) RT1 = 1 RT0 = 0 83.75 84.25 uS 4) RT1 = 1 RT0 = 1 147.75 148.25 uS t55 HALTREQN setup for next message wrt to INCMDN ↑ 150 nS t56 R/WN ↓ to R/WN ↓ RT-BC Report cycle 80t t57 BUFENN ↑ to BUFENN ↓ Data word to report word 29t t58 BC intermessage gap 1) without a No Operation instruction 20 uS 2) with a No Operation instruction 28 uS t59 CODENN interval high between received status 24t and report word during report cycle t60 CODENN interval between report word and 6t next message fetch for continuous operation t61 CODEN interval between BC Noop data pointer fetch and report word 5t t62 INCMDN ↑ to INCADDRN ↓ 1t t63 BUSYREQN ↓ to BUSYACKN ↓ 60 nS t64 BUSYREQN ↑ to BUSYACKN ↑ 60 nS t65 INCMDN ↑ to BUSYACKN ↓ 60 nS t66 INCMDN ↑ to BUSYACKN ↑ 100 nS t67 CK4 ↑ to R/WN/BUFENN/CO/C1/CODENN/MDTN 115 nS Mil-Std-883, method 5005, subgroups 9, 10, 11 Notes: 1. t = CK4 period, t12 = CK12 period 2. Times quoted as typical means a fixed number of CK4 clock cycles but excludes slight variations due to propagation delays. Conditions: Vdd = 4.5 to 5.5V, Tamb = -55°C to +125°C, VIL = 0V, VIH = 4V, VOUT Threshold = 1.5V except t2 where measured by a 1V change in output voltage. Load = 50pf except t2 where additional 1K load to 0V or VDD. Figure 12: AC Electrical Characteristics (continued) |
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