L9822E

Functional description

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4.4

Output stages

The output stages provide an active low drive signal suitable for 0.75 A continuous loads.

Each output has a current limit circuit which limits the maximum output current to at least

1.05A to allow for high inrush currents. Additionally, the outputs have internal zeners set to

36 volts to clamp inductive transients at turn-off. Each output also has a voltage comparator

observing the output node. If the voltage exceeds 1.8 V on an ON output pin, a fault

condition is assumed and the latch driving this particular stage is reset, turning the output

OFF to protect it. The timing of this action is described below. These comparators also

provide diagnostic feedback data to the shift register. Additionally, the comparators contain

an internal pulldown current which will cause the cell to indicate a low output voltage if the

output is programmed OFF and the output pin is open circuited.

4.5

Timing data transfer

Figure 5 shows the overall timing diagram from a byte transfer to and from the L9822E using

the SPI bus.

4.5.1

CE high to low transition

The action begins when the Chip Enable (CE) pin is pulled low. The tri-state Serial Output

(SO) pin driver will be enabled entire time that CE is low. At the falling edge of the CE pin,

the diagnostic data from the voltage comparators in the output stages will be latched into the

shift register. If a particular output is high, a logic one will be jammed into that bit in the shift

register. If the output is low, a logic zero will be loaded there. The most significant bit (07)

should be presented at the Serial Input (SI) pin. A zero at this pin will program an output ON,

while a one will program the output OFF.

4.5.2

SCLK transitions

The Serial Clock (SCLK) pin should then be pulled high. At this point the diagnostic bit from

the most significant output (07) will appear at the SO pin. A high here indicates that the 07

pin is higher than 1.8 V. The SCLK pin should then be toggled low then high. New SO data

will appear following every rising edge of SCLK and new SI data will be latched into the

L9822E shift register on the falling edges. An unlimited amount of data may be shifted

through the device shift register (into the SI pin and out the SO pin), allowing the other SPI

devices to be cascaded in a daisy chain with the L9822E.

4.5.3

CE low to high transition

Once the last data bit has been shifted into the L9822E, the CE pin should be pulled high. At

the rising edge of CE the shift register data is latched into the parallel latch and the output

stages will be actuated by the new data. An internal 160 µs delay timer will also be started at

analog current limiting circuits since the resetting of the parallel latches by faults conditions

will be inhibited during this period.

This allows the part to overcome any high inrush currents that may flow immediately after

turn on. Once the delay period has elapsed, the output voltages are sensed by the

comparators and any output with voltages higher than 1.8 V are latched OFF. It should be

noted that the SCLK pin should be low at both transitions of the CE pin to avoid any false

clocking of the shift register. The SCLK input is gated by the CE pin, so that the SCLK pin is

ignored whenever the CE pin is high.