ADS8341_14 datasheet(15/25 Pages) TI1

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ADS8341

SBAS136D

FIGURE 8. Supply Current versus Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping

DCLK at the Maximum Possible Frequency.

FIGURE 9. Supply Current versus State of CS.

10k

100k

SAMPLE (Hz)

100

1000

CLK = 2.4MHz

CLK = 24 • fSAMPLE

A = 25°C

CC = +2.7V

REF = +2.5V

PD1 = PD0 = 0

10k

100k

SAMPLE (Hz)

0.00

0.09

CS LOW

(GND)

CS HIGH (+V

CC)

A = 25°C

CC = +2.7V

REF = +2.5V

CLK = 24 • fSAMPLE

PD1 = PD0 = 0

FIGURE 7. Ideal Input Voltages and Output Codes.

Data Format

The ADS8341 output data is in straight binary format, as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

Operating the ADS8341 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

FS = Full-Scale Voltage = V

REF

1LSB = V

REF/65,536

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

NOTE(1): Voltage at converter input, after

multiplexer: +IN – (–IN). (See Figure 2.)

Input Voltage(1) (V)

POWER DISSIPATION

There are three power modes for the ADS8341: full power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The affects of these modes

varies depending on how the ADS8341 is being operated.

For example, at full conversion rate and 24-clocks per

conversion, there is very little difference between full power

mode and auto power-down, a shutdown (SHDN LOW) will

not lower power dissipation.

When operating at full-speed and 24-clocks per conversion

(as shown in Figure 3), the ADS8341 spends most of its time

acquiring or converting. There is little time for auto power-

down, assuming that this mode is active. Thus, the differ-

ence between full power mode and auto power-down is

negligible. If the conversion rate is decreased by simply

slowing the frequency of the DCLK input, the two modes

remain approximately equal. However, if the DCLK fre-

quency is kept at the maximum rate during a conversion, but

conversion are simply done less often, then the difference

between the two modes is dramatic. Figure 8 shows the

difference between reducing the DCLK frequency (“scal-

ing” DCLK to match the conversion rate) or maintaining

DCLK at the highest frequency and reducing the number of

conversion per second. In the later case, the converter

spends an increasing percentage of its time in power-down

mode (assuming the auto power-down mode is active).

If DCLK is active and CS is LOW while the ADS8341 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH. The differences in

supply current for these two cases are shown in Figure 9.

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