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ICS1523MLF データシート(PDF) 16 Page - Integrated Circuit Systems

部品番号 ICS1523MLF
部品情報  Video Clock Synthesizer with I2C Programmable Delay
PDF  21 Pages
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メーカー  ICST [Integrated Circuit Systems]
ホームページ  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1523MLF データシート(HTML) 16 Page - Integrated Circuit Systems

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Video Clock Synthesizer with I2C Programmable Delay
ICS1523
MDS 1523 Y
16
Revision 110905
Integrated Circuit Systems
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
12.2 Timing for 0x0:2=1
Figure 12-3 0x0:2=1 Timing Diagram
Table 12-3
0x0:2=1 Timing Values
Symbol Parameter
Minimum
Typical
Maximum
Units
T2
HSYNC Low to FUNC High Delay
T8 + T3
ns
T3
HSYNC Low to PECL CLK+ High Delay
(DPA Offset = 0)
-10
-
ns
T4
PECL Clock to SSTL_3 Clock Delay
0
0.2
0.6
ns
T5
PECL Clock to FUNC Delay
0.6
1.0
1.6
ns
T6
PECL Clock to PECL/2 Clock
0.6
1.0
1.6
ns
T7
PECL Clock to SSTL_3 CLK/2 Delay
0.4
0.9
1.2
ns
T8
PECL Clock High Time
-
0.5
-
UI



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