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IDT7133LA55JI データシート(PDF) 13 Page - Integrated Device Technology

部品番号 IDT7133LA55JI
部品情報  HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
PDF  16 Pages
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7133LA55JI データシート(HTML) 13 Page - Integrated Device Technology

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6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
13
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform of BUSY Arbitration Controlled by Addresses(1)
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the
BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(IDT7133 only).
tAPS(2)
2746 drw 13
ADDR"A" AND "B"
ADDRESSES MATCH
CE"B"
BUSY"B"
tBAC
tBDC
CE"A"
tRC
2746 drw 14
ADDR "A"
ADDRESSES MATCH
ADDR "B"
BUSY "B"
ADDRESSES DO NOT MATCH
tWC
OR
tAPS
tBAA
tBDA
(2)



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