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376 データシート(PDF) 48 Page - Intel Corporation |
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376 データシート(HTML) 48 Page - Intel Corporation |
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48 / 95 page  376 EMBEDDED PROCESSOR 240182 – 26 Figure 411 Details of Address Pipelining during Cycles with Wait States T1 – T2 – T2P are the states of the bus cycle that es- tablishes address pipelining for the next bus cycle which begins with T1P The same is true after a bus hold state shown below Th Th Th T1 – T2 – T2P T1P – T2P hold aknowledge non-pipelined pipelined states cycle cycle The transition to pipelined address is shown func- tionally by Figure 410 Cycle 1 Note that Cycle 1 is used to transition into pipelined address timing for the subsequent Cycles 2 3 and 4 which are pipe- lined The NA input is asserted at the appropriate time to select address pipelining for Cycles 2 3 and 4 Once a bus cycle is in progress and the current ad- dress and status has been valid for one entire bus state the NA input is sampled at the end of every phase one until the bus cycle is acknowledged 48 |
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