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CDP1802BCEX データシート(PDF) 12 Page - Intersil Corporation |
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CDP1802BCEX データシート(HTML) 12 Page - Intersil Corporation |
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12 / 27 page ![]() 3-14 FIGURE 8. MEMORY READ CYCLE TIMING WAVEFORMS FIGURE 9. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) MEMORY READ CYCLE MEMORY READ CYCLE MEMORY READ CYCLE INSTRUCTION FETCH (S0) EXECUTE (S1) FETCH (S0) EXECUTE MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT MRD MWR (HIGH) “DON’T CARE” OR INTERNAL DELAYS HIGH IMPEDANCE STATE VALID OUTPUT MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID OUTPUT MEMORY READ CYCLE MEMORY READ CYCLE MEMORY READ CYCLE INSTRUCTION FETCH (S0) EXECUTE (S1) EXECUTE (S1) FETCH (S0) MRD MWR (HIGH) “DON’T CARE” OR INTERNAL DELAYS HIGH IMPEDANCE STATE VALID OUTPUT CDP1802A, CDP1802AC, CDP1802BC |
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