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ADE7569 データシート(PDF) 48 Page - Analog Devices |
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ADE7569 データシート(HTML) 48 Page - Analog Devices |
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48 / 152 page  ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 48 of 152 Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) Bit Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled by clearing Bit 2 of the MODE1 register. 6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not enabled by clearing Bit 1 of the MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full. 1 REHF1 Logic 1 indicates that the VARHR register is half full. 0 AEHF Logic 1 indicates that the WATTHR register is half full. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) Bit Interrupt Flag Description 7 RESET Indicates the end of a reset (for both software and hardware reset). 6 Reserved Reserved. 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value. 3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel. Table 43. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9) Bit Interrupt Enable Bit Description [7:6] Reserved Reserved. 5 FAULTSIGN1 When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core. 4 VARSIGN2 When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 RNOLOAD2 When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 or ADE7569. 2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA) Bit Interrupt Enable Bit Description 7 CF2 When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. 4 REOF1 When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. 1 REHF1 When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core. 0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. |
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