ADF4106BRUZ-R7 datasheet(11/24 Pages) AD

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Data Sheet

ADF4106

Rev. E | Page 11 of 24

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter

(N = BP + A) and produces an output proportional to the

phase and frequency difference between them. Figure 20 is a

simplified schematic. The PFD includes a programmable delay

element that controls the width of the antibacklash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. Two

bits in the reference counter latch, ABP2 and ABP1, control the

width of the pulse. See Table 7.

CLR2

DOWN

ABP2

ABP1

CPGND

R DIVIDER

PROGRAMMABLE

DELAY

N DIVIDER

CHARGE

PUMP

CLR1

Figure 20. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4106 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Table 9 shows the full truth table. Figure 21 shows the

MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase

error on three consecutive phase detector cycles is less than

15 ns. With LDP set to 1, five consecutive cycles of less than

15 ns are required to set the lock detect. It stays set high until a

phase error of greater than 25 ns is detected on any subsequent

PD cycle.

The N-channel, open-drain, analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock is detected, this output is high with narrow, low-

going pulses.

DGND

DVDD

CONTROL

MUX

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUXOUT

Figure 21. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF4106 digital section includes a 24-bit input shift

6-bit A counter and a 13-bit B counter. Data is clocked into the

24-bit shift register on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the shift register

to one of four latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. These are the two LSBs, DB1 and DB0, as

shown in the timing diagram of Figure 2. The truth table for

these bits is shown in Table 5. Table 6 shows a summary of how

the latches are programmed.

Table 5. C1, C2 Truth Table

Control Bits

Data Latch

R Counter

N Counter (A and B)

Function Latch (Including Prescaler)

Initialization Latch

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