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AN3147

Run and low power modes

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4.7

Low power run mode

This mode is based on code execution from RAM, using a low speed clock source. The

main voltage regulator (MVR) is switched off and the low power voltage regulator (LPVR) is

used to supply the voltage to internal structures. The Flash memory is configured by

The ADC is not supported in this mode, as its clock source must have a minimum frequency

of 1 MHz.

No interrupt is allowed in this mode as the interrupt vectors are located in the Flash (which is

switched off). Consequently, all interrupts must be masked.

While using this mode, you have to switch from high speed clock sources to low speed clock

sources.

Note:

This mode is not available on the STM8L101xx devices.

4.7.1

Entering Low power run mode

This mode is entered by executing the following software sequence:

1.

Switch off all unused peripherals, oscillators (except LSI or LSE) and analog blocks

2.

Mask all interrupts

3.

Jump to RAM

4.

Switch system clock to LSI or LSE clock sources

5.

register

6.

Add a software delay loop to make sure the Flash/Data EEPROM are off

7.

Configure the ultralow power mode for the regulator by setting the REGOFF bit in the

CLK_REGCSR register (do not confuse with the ULP bit in the PWR_CSR2 which

configures the behavior of the internal reference voltage).

Steps 1 to 4 can be performed in any order.

4.7.2

Exiting Low power run mode

The only way to exit this mode is to follow these steps:

1.

Switch on the main regulator by resetting the REGOFF bit in the CLK_REGCSR

register. The REGREADY flag in the CLK_REGCSR register is set when the regulator

is ready.

2.

Switch on the Flash/Data EEPROM by resetting the EEPM bit in the FLASH_CR1

register. The EEREADY flag in the CLK_REGCSR register is set when the Flash/Data

EEPROM is ready.

3.

Switch the clock to HSI (or HSE).

4.

Reset interrupt mask.

5.

Switch on what is necessary and jump to Flash/Data EEPROM if needed.