DocID17035 Rev 3

19/25

AN3147

Run and low power modes

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4.9.2

Exiting Halt mode

Wakeup from Halt mode is triggered by an external interrupt, sourced by a general purpose

I/O port configured as interrupt input or by an alternate function pin capable of triggering a

peripheral interrupt.

The system clock is then restarted at a frequency depending on the FHW bit in the

CLK_ICKCR register. If the FHW bit is set, HSI/8 is the system clock. Otherwise, the system

clock is the last selected clock source before the system enters Halt mode.

Note:

When the STM8L101xx microcontroller is woken up from Halt mode, the same clock source

as that used before entering this mode is always selected.

In an interrupt-based application, where most of the processing is done through the interrupt

routines, the main program may be suspended by setting the activation level bit (AL) in the

CFG_GCR register. Refer to Section 4.10: Activation level control on page 19.

4.9.3

Active-halt mode

In Active-halt mode, the main oscillator, the CPU and almost all peripherals are stopped.

Only the LSI RC oscillator or the LSE crystal is running to drive the SWIM, beep, IWDG,

RTC and LCD, if enabled. The user can enter this mode by a HALT instruction, once some

of the peripherals above have been enabled.

4.10

Activation level control

The STM8L/STM8AL devices support an automatic activation level control feature.

Consequently, the user can configure the MCU so that it directly returns to a low power

mode after it has been woken up from such a mode through interrupts.

In an interrupt-based application, where most of the processing is done through the interrupt

routines, the main program may be suspended by setting the activation level bit (AL) in the

CFG_GCR register. Setting this bit causes the CPU to return to low power mode after

exiting an interrupt service routine without restoring the main execution context when the

IRET instruction is executed. This saves power by removing both the save/restore context

activity and the need for a main software loop execution for power management (in order to

return to low power mode).

To return to the main loop, the AL bit has to be cleared by software. This must be done at

least two clock cycles before the IRET instruction is executed.