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Advanced features for motor control

AN4013

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The dead time delay is computed using the following formula:

Dead time = DTG[7:0]x Tdtg, if DTG[7] = 0

Dead time = (64+DTG[5:0]) x Tdtg, if DTG[6] = 0

Dead time = (32+DTG[4:0]) x Tdtg, if DTG[5] = 0

Dead time = (32+DTG[4:0]) x Tdtg, if DTG[7:5] = 111

For more details on using the timer in this mode, refer to the examples provided in the

STM32xx standard peripheral libraries, in the /Project/STM32xx_StdPeriph_Examples/

TIM/ComplementarySignals folder.

STM32Cube F3 firmware includes package examples in the following directories:



Projects\STM32F3-Discovery\Examples\TIM\TIM_ComplementarySignals,



Projects\STM32373C_EVAL\Examples\TIM\TIM_ComplementarySignals,



Projects\STM32303E_EVAL\Examples\TIM\TIM_ComplementarySignals,



Projects\STM32303C_EVAL\Examples\TIM\TIM_Combined.

Note:

This example is not available for STM32L1 series.

4.3.2

Break input

The break input is an emergency input in the motor control application. The break function

protects power switches driven by PWM signals generated with the advanced timers. The

break input is usually connected to fault outputs of power stages and 3-phase inverters.

When activated, the break circuitry shuts down the TIM outputs and forces them to a

predefined safe state.

The break event is generated by:



The BRK input that has a programmable polarity and an enable bit BKE.



The CSS (Clock Security System).



Software, by setting the BG bit in the EGR register.

When a break event occurs:



The MOE bit (main output enable) is cleared.



The break status flag is set and an interrupt request can be generated.



Each output channel is driven with the level programmed in the OISx bit.

Break inputs in STM32F30x and STM32F3x8

In these lines there are two break inputs Break1 and Break2. The break can be generated

by any of the two BRK inputs which have:



a programmable polarity (BKPx bit in the TIMx_BDTR Register)



a programmable enable bit (BKEx in the TIMx_BDTR Register)



a programmable filter (BKxF[3:0] bits in the TIMx_BDTR Register) to avoid spurious

events.

The following table presents the priorities between the two break inputs.

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