RM0312 datasheet(138/275 Pages) STMICROELECTRONICS

138 / 275 page

16-bit general purpose timer (TIM2/TIM3)

RM0312

138/275

DocID022352 Rev 3

The OPM waveform is defined by writing the compare registers (taking into account the

clock frequency and the counter prescaler).

•

The tDELAY is defined by the value written in the TIMx_CCR1 register.

•

The tPULSE is defined by the difference between the auto-reload value and the compare

value (TIMx_ARR - TIMx_CCR1).

•

Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare

match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload

value. To do this you enable PWM mode 2 by writing OCiM=0b111 in the TIMx_CCMR1

TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to

write the compare value in the TIMx_CCR1 register, the auto-reload value in the

TIMx_ARR register, generate an update by setting the UG bit and wait for external

trigger event on TI2. CC1P is written to ‘0’ in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the

counter at the next update event (when the counter rolls over from the auto-reload value

back to 0).

Particular case: OCi fast enable:

In One Pulse Mode, the edge detection on TIi input set the CEN bit which enables the

counter. Then the comparison between the counter and the compare value makes the

output toggle. But several clock cycles are needed for these operations and it limits the

minimum delay tDELAY min we can get.

If you want to output a waveform with the minimum delay, you can set the OCiFE bit in the

TIMx_CCMRi register. Then OCiREF (and OCi) will be forced in response to the stimulus,

without taking in account the comparison. Its new level will be the same as if a compare

match had occured. OCiFE acts only if the channel is configured in PWM1 or PWM2 mode.

17.5.8

Using the break function

The break function is often used in motor control. When using the break function, the output

enable signals and inactive levels are modified according to additional control bits (MOE,

OSSR and OSSI bits in the TIMx_BKR register).

When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable

the break function by setting the BKE bit in the TIMx_BKR register. The break input polarity

can be selected by configuring the BKP bit in the same register. BKE and BKP can be

modified at the same time.

Because MOE falling edge can be asynchronous, a resynchronization circuit has been

inserted between the actual signal (acting on the outputs) and the synchronous control bit

(accessed in the TIMx_BKR register). It results in some delays between the asynchronous

and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you

must insert a delay (dummy instruction) before reading it correctly.

RM0312 データシート(PDF) 138 Page - STMicroelectronics

RM0312 データシート(HTML) 138 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード