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RM0312 データシート(PDF) 168 Page - STMicroelectronics |
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RM0312 データシート(HTML) 168 Page - STMicroelectronics |
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168 / 275 page  8-bit basic timer (TIM4) RM0312 168/275 DocID022352 Rev 3 18.5.4 Interrupt enable register (TIM4_IER) Address offset: 0x03 Reset value: 0x00 18.5.5 Status register 1 (TIM4_SR1) Address offset: 0x04 Reset value: 0x00 7 654 3210 Reserved TIE Reserved UIE rw rw Bit 7 Reserved Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bits 5:1 Reserved Bit 0 UIE: Update Interrupt Enable 0: Update Interrupt disabled 1: Update Interrupt enabled 7 654 3210 Reserved TIF Reserved UIF rc_w0 rc_w0 Bit 7 Reserved Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI signal, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bits 5:1 Reserved Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – at overflow if UDIS=0 in the TIM4_CR1 register. – when CNT is re-initialized by software using the UG bit in the TIM4_EGR register, if URS=0 and UDIS=0 in the TIM4_CR1 register. |
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