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RM0312 データシート(PDF) 252 Page - STMicroelectronics |
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RM0312 データシート(HTML) 252 Page - STMicroelectronics |
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252 / 275 page  ProxSense™ (PXS) RM0312 252/275 DocID022352 Rev 3 Figure 95. ProxSense block diagram There are 15 transmit outputs (m = 0 to 14) and up to 10 receivers (n = 0 to 9), each cell having 2 PXS_RX pins (A and B). 22.4.2 ProxSense charge transfer sequence A ProxSense acquisition consists of a series of charge transfers, each of which is divided into an UP phase and a PASS phase. The acquisition result is the number of charge transfers which are necessary to cause the internal capacitor (Cs), which receives each of the charge transfers, to reach the threshold voltage. The events which occur during the UP and PASS phases are defined in Table 54. CNT[15:0] n PXS_RXA n PXS_TX m Enable m n n n MAXEN[15:0] n n n PXS_TRIG PXS_VREG Noise Detector Voltage Regulator PXS Clock PXS Ctrl MS18159V1 PXS_RFIN PXS_RXB n EPCC PXS_RXSR PXS_RXENR PXS_RXINSR PXS_RXCR1 PXS_RXCR2 PXS_RXCR3 PXS_RXMAXENR Acquisition Receive Cell n Valid counter value n Acquisition Transmit Cell m PXS_OSC 16 MHz PXS_RX nCNTR PXS_RXMAXR PXS_RX nCSSELR PXS_RX nEPCCSELR Enable Inactive state Mode/Function Maximum Enable Maximum Value CS ProxSense Controller Prescaler PXS_TXENR PXS_CR1 PXS_CR2 PXS_CR3 PXS_SR PXS_CKCR1 PXS_CKCR2 Table 54. Activities during the UP and PASS phases Mode UP phase PASS phase Projected capacitance – Tx line forced low – Rx line held at sampled voltage (sampled at end of previous PASS phase). – Tx line forced high – Cs absorbs the charge transferred to the Rx line through the projected capacitance. |
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