PYA28HC256 datasheet(3/15 Pages) PYRAMID

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PYA28HC256 - HIGH SPEED 32K x 8 EEPROM

Page 3

Document # EEPROM106 REV 03

three write commands; three specific bytes of data are

written to the three specific addresses (refer to "Software

Data Protection" algorithm). After writing the 3-byte com-

mand sequence and after tWC the entire PYA28C256

will be protected against inadvertent write operations. It

should be noted, that once protected the host may still

perform a byte or page write to the PYA28C256. This

is done by preceding the data to be written by the same

3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable com-

mand sequence is issued. Power transitions do not dis-

able SDP and SDP will protect the PYA28C256 during

power-up and power-down conditions. All command se-

quences must conform to the page write timing specifi-

cations. The data in the enable and disable command

sequences is not written to the device and the memory

addresses used in the sequence may be written with data

in either a byte or page write operation.

After setting SDP, any attempt to write to the device with-

out the 3-byte command sequence will start the internal

write timers. No data will be written to the device; howev-

er, for the duration of tWC, read operations will effectively

be polling operations.

DEVICE IDEnTIFICATIOn

An extra 64 bytes of EEPROM memory are available to

the user for device identification. By raising A9 to 12V

± 0.5V and using address locations 7FC0H to 7FFFH

the additional bytes may be written to or read from in the

same manner as the regular memory array.

OPTIOnAL CHIP ERASE MODE

The entire device can be erased using a 6-byte software

code. Please see "Software Chip Erase" application note

at the end of this datasheet for details.

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