-

=

´

OUT

VFB

VFB

V

V

R1

R2

V

+

=

+

INJ _ SW

INJ _ OUT

VFB

V

V

V

0.6

2

(

)

(

)

=

´

+

´

´

IND ripple

INJ _ OUT

IND ripple

OUT

SW

I

V

ESR I

8 C

f

-

=

´

´

IN

OUT

INJ _ SW

SW

V

V

D

V

R7 C1

f

´

>

´

´

OUT

ON

L

C

t

N

R7

C1

2

TPS53353

www.ti.com

SLUSAK2B – AUGUST 2011 – REVISED FEBRUARY 2015

where

•

(16)

capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may

have only 8 µF of effective capacitance when biased at 5 V.

Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase

of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node

and the other coupled from the VOUT pin and they can be calculated using Equation 17 and Equation 18 when

neglecting the output voltage ripple caused by equivalent series inductance (ESL).

(17)

(18)

The DC voltage at the VFB pin can be calculated by Equation 19:

(19)

And the resistor divider value can be determined by Equation 20:

(20)

8.2.2.3 Application Curves

Figure 42. Enable Turnon

Figure 43. Enable Turnoff

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