VFB

EN

PGOOD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

GND

PowerPad

TM

18

19

20

21

22

VBST

TRIP

MODE

N/C

LL

LL

LL

LL

LL

LL

RF

VDD

VREG

VIN

VIN

VIN

VIN

VIN

VIN

TPS53353

www.ti.com

SLUSAK2B – AUGUST 2011 – REVISED FEBRUARY 2015

5 Pin Configuration and Functions

DQP Package

22-Pins LSON-CLIP

Top View

(1)

N/C = no connection

Pin Functions

PIN

DESCRIPTION

NAME

NO.

EN

2

I

Enable pin.Typical turnon threshold voltage is 1.2 V. Typical turnoff threshold voltage is 0.95 V.

GND

G

Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.

6

7

8

LL

B

Output of converted power. Connect this pin to the output Inductor.

9

10

11

Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 3. The soft-start

MODE

20

I

time is detected and stored into internal register during start-up.

N/C

5

No connect.

Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB

PGOOD

3

O

goes out of the specified limits PGOOD goes low after a 2-µs delay

Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using

RF

22

I

Table 1. The switching frequency is detected and stored during the startup.

and set the OCL trip voltage as follows.

TRIP

21

I

Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node.

VBST

4

P

Internally connected to VREG via bootstrap MOSFET switch.

VDD

19

P

Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.

VFB

1

I

Output feedback input. Connect this pin to Vout through a resistor divider.

12

13

14

VIN

P

Conversion power input.The conversion input voltage range is from 1.5 V to 15 V.

15

16

17

VREG

18

P

5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.

(1)

I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground

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