AR0330 datasheet(12/77 Pages) ONSEMI

12 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Pin Descriptions

Table 5:

Pin Descriptions

Name

Type

Description

RESET_BAR

Input

Asynchronous reset (active LOW). All settings are restored to factory default.

EXTCLK

Input

Master input clock, range 6 -27 MHz

OE_BAR

Input

Output enable (active LOW). Only available on bare die version.

TRIGGER

Input

Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame.

SADDR

Input

Two-wire serial address select.

SCLK

Input

Two-wire serial clock input.

SDATA

I/O

Two-wire serial data I/O.

PIXCLK

Output

Pixel clock out. DOUT is valid on rising edge of this clock.

DOUT[11:0]

Output

Parallel pixel data output.

FLASH

Output

Flash output. Synchronization pulse for external light source. Can be left floating if not used.

FRAME_VALID

Output

Asserted when DOUT data is valid.

LINE_VALID

Output

Asserted when DOUT data is valid.

VDD

Power

Digital power.

VDD_IO

Power

IO supply power.

VDD_PLL

Power

PLL power supply. The MIPI power supply (VDD_MIPI) is tied to VDD_PLL in both packages.

DGND

Power

Digital GND.

VAA

Power

Analog power.

VAA_PIX

Power

Pixel power.

AGND

Power

Analog GND.

TEST

Input

Enable manufacturing test modes. Tie to DGND for normal sensor operation.

SHUTTER

Output

Control for external mechanical shutter. Can be left floating if not used.

SLVS0_P

Output

HiSPi serial data, lane 0, differential P.

SLVS0_N

Output

HiSPi serial data, lane 0, differential N.

SLVS1_P

Output

HiSPi serial data, lane 1, differential P.

SLVS1_N

Output

HiSPi serial data, lane 1, differential N.

SLVS2_P

Output

HiSPi serial data, lane 2, differential P.

SLVS2_N

Output

HiSPi serial data, lane 2, differential N.

SLVS3_P

Output

HiSPi serial data, lane 3, differential P.

SLVS3_N

Output

HiSPi serial data, lane 3, differential N.

SLVSC_P

Output

HiSPi serial DDR clock differential P.

SLVSC_N

Output

HiSPi serial DDR clock differential N.

DATA1_P

Output

MIPI serial data, lane 1, differential P

DATA1_N

Output

MIPI serial data, lane 1, differential N

DATA2_P

Output

MIPI serial data, lane 2, differential P

DATA2_N

Output

MIPI serial data, lane 2, differential N

DATA3_P

Output

MIPI serial data, lane 3, differential P

DATA3_N

Output

MIPI serial data, lane 3, differential N

DATA4_P

Output

MIPI serial data, lane 4, differential P

DATA4_N

Output

MIPI serial data, lane 4, differential N

CLK_P

Output

Output MIPI serial clock, differential P

CLK_N

Output

Output MIPI serial clock, differential N

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