CS5304 datasheet(13/19 Pages) ONSEMI

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CS5304

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SWNODE

VFB (VOUT)

CSA Out

CSA Out + VFB

Figure 10. Open Loop Operation

COMP − Offset

Inductive Current Sensing

For lossless sensing, current can be sensed across the

inductor as shown in Figure 11. In the diagram L is the output

inductance and RL is the inherent inductor resistance. To

compensate the current sense signal the values of R1 and C1

are chosen so that L/RL = R1 × C1. If this criteria is met the

current sense signal will be the same shape as the inductor

current, the voltage signal at CSx will represent the

instantaneous value of inductor current and the circuit can be

analyzed as if a sense resistor of value RL was used as a sense

resistor (RS).

SWNODE

VOUT

DACOUT

COMP

VFB

CSREF

CSX

CSA

OFFSET

PWM-

COMP

E.A.

Figure 11. Lossless Inductive Current Sensing with

Enhanced V2

When choosing or designing inductors for use with

inductive sensing tolerances and temperature effects should

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per

°C. The increase in

winding resistance at higher temperatures should be

considered when setting the ILIM threshold. If a more

accurate current sense is required than inductive sensing can

provide, current can be sensed through a resistor as shown

in Figure 9.

Current Sharing Accuracy

PCB traces that carry inductor current can be used as part

of the current sense resistance depending on where the

current sense signal is picked off. For accurate current

sharing, the current sense inputs should sense the current at

the same point for each phase and the connection to the

CSREF should be made so that no phase is favored. (In some

cases, especially with inductive sensing, resistance of the

pcb can be useful for increasing the current sense

resistance.) The total current sense resistance used for

calculations must include any pcb trace between the CSx

inputs and the CSREF input that carries inductor current.

Current Sense Amplifier Input Mismatch and the value of

the current sense element will determine the accuracy of

current sharing between phases. The worst case Current

Sense Amplifier Input Mismatch is 5.0 mV and will

typically be within 3.0 mV. The difference in peak currents

between phases will be the CSA Input Mismatch divided by

the current sense resistance. If all current sense elements are

of equal resistance a 3.0 mV mismatch with a 2.0 m

W sense

resistance will produce a 1.5 A difference in current between

phases.

Operation at > 50% Duty Cycle

For operation at duty cycles above 50% Enhanced V2 will

exhibit subharmonic oscillation unless a compensation

ramp is added to each phase. A circuit like the one on the left

side of Figure 12 can be added to each current sense network

to implement slope compensation. The value of R1 can be

varied to adjust the ramp size.

Switch Node

CSX

CSREF

25 k

.01

1.0 nF

0.1

3.0 k

Gate(L)X

Slope Comp

Circuit

Existing Current

Sense Circuit

MMBT2222LT1

Figure 12. External Slope Compensation Circuit

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