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CS5307GDWR24 データシート(PDF) 17 Page - ON Semiconductor |
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CS5307GDWR24 データシート(HTML) 17 Page - ON Semiconductor |
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17 / 24 page ![]() CS5307 http://onsemi.com 17 For decreasing current: DtDEC + Lo @ DIO (VOUT) (3.2) For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. Thus, it may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied and excessive overshoot may result. The output voltage ripple can be calculated using the output inductor value derived in this Section (LoMIN), the number of output capacitors (NOUT,MIN) and the per capacitor ESR determined in the previous Section: VOUT,P−P + (ESR per cap NOUT,MIN) @ (VIN * #Phases @ VOUT) @ D (LoMIN @ fSW) (4) This formula assumes steady−state conditions with no more than one phase on at any time. The second term in Equation 4 is the total ripple current seen by the output capacitors. The total output ripple current is the “time summation” of the four individual phase currents that are 90 degrees out−of−phase. As the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. Therefore, the total output ripple current and voltage are reduced in a multi−phase converter. 3. Input Capacitor Selection The choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst case input voltage with adequate margin. To calculate the number of input capacitors, one must first determine the total RMS input ripple current. To this end, begin by calculating the average input current to the converter: IIN,AVG + IO,MAX @ D h (5) where: D is the duty cycle of the converter, D = VOUT/VIN; η is the specified minimum efficiency; IO,MAX is the maximum converter output current. The input capacitors will discharge when the control FET is ON and charge when the control FET is OFF as shown in Figure 21. The following equations will determine the maximum and minimum currents delivered by the input capacitors: IC,MAX + ILo,MAX h * IIN,AVG (6) IC,MIN + ILo,MIN h * IIN,AVG (7) ILo,MAX is the maximum output inductor current: ILo,MAX + IO,MAX 4 ) DILo 2 (8) ILo,MIN is the minimum output inductor current: ILo,MIN + IO,MAX 4 * DILo 2 (9) ΔILo is the peak−to−peak ripple current in the output inductor of value Lo: DILo + (VIN * VOUT) @ D (Lo @ fSW) (10) For the four−phase converter, the input capacitor(s) RMS current is then: ICIN,RMS + [4D @ (IC,MIN2 ) IC,MIN @ DIC,IN ) DIC,IN2 3) ) IIN,AVG2 @ (1 * 4D)]1 2 (11) Select the number of input capacitors (NIN) to provide the RMS input current (ICIN,RMS) based on the RMS ripple current rating per capacitor (IRMS,RATED): NIN + ICIN,RMS IRMS,RATED (12) For a four−phase converter with perfect efficiency (η = 1), the worst case input ripple−current will occur when the converter is operating at a 12.5% duty cycle. At this operating point, the parallel combination of input capacitors must support an RMS ripple current equal to 12.5% of the converter’s DC output current. At other duty cycles, the ripple−current will be less. For example, at a duty cycle of either 6% or 19%, the four−phase input ripple−current will be approximately 10% of the converter’s DC output current. In general, capacitor manufacturers require derating to the specified ripple−current based on the ambient temperature. More capacitors will be required because of the current derating. The designer should know the ESR of the input capacitors. The input capacitor power loss can be calculated from: PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13) Low ESR capacitors are recommended to minimize losses and reduce capacitor heating. The life of an electrolytic capacitor is reduced 50% for every 10°C rise in the capacitor’s temperature. IC,MAX IC,MIN 0 A −IIN,AVG FET On, Caps Discharging FET Off, Caps Charging tON T/4 ΔIC,IN = IC,MAX − IC,MIN Figure 21. Input Capacitor Current for a Four−Phase Converter |
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