CS5307GDWR24 datasheet(21/24 Pages) ONSEMI

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CS5307

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−

RCS1

CS1

CCS1

IMAX/2

GVDRP

−

RCSx

CSx

CCSx

IMAX/2

GVDRP

CSREF

COMP

Error

Amp

VID Setting

IBIASVFB

RDRP

RFB

VDRP = VID +

IMAX • RL • GVDRP

VFB = VID

VCORE

IDRP

IFB

VCORE = VID − (IDRP − IBIASVFB) w RFB

Figure 25. AVP Circuitry at Full−Load

IDRP = IMAX • RL • GVDRP/RDRP

IFBK = IDRP − IBIASVFB

= VID − IMAX w RL w GVDRP w RFB/RDRP + IBIASVFB w RFB

+ −

Figure 26. VDRP Tuning Waveforms. The RC Time

Constant of the Current Sense Network Is Too Long

(Slow): VDRP and VOUT Respond Too Slowly.

Figure 27. VDRP Tuning Waveforms. The RC Time

Constant of the Current Sense Network Is Too Short

(Fast): VDRP and VOUT Both Overshoot.

Resistor RDRP is connected between the VDRP and the

VFB pins. At no−load, the VDRP and the VFB pins will both

be at the DAC voltage. This resistor will conduct zero

current. However, at full−load, the voltage at the VDRP pin

will increase proportional to the output inductor’s current

while VFB will still be regulated to the DAC voltage. Current

will be conducted from VDRP to VFB by RDRP. This current

will be large enough to supply the VFB bias current and cause

a voltage drop from VFB to VCORE across RFB. The

converter’s output voltage will be reduced. This condition is

shown in Figure 25.

To determine the value of RDRP, the designer must specify

the full−load voltage reduction from the VID (DAC) setting

(ΔVOUT,FULL−LOAD) and predict the voltage increase at the

VDRP pin at full−load. Usually, the full−load voltage

reduction is specified in the design guide for the processor

that is available from the manufacturer. To predict the

voltage increase at the VDRP pin at full−load (ΔVDRP), the

designer must consider the output inductor’s resistance

(RL), the PCB trace resistance between the current sense

points (RPCB) and the controller IC’s gain from the current

sense to the VDRP pin (GVDRP):

DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP (30)

The value of RDRP can then be calculated:

RDRP +

DVDRP

(IBIASVFB ) DVOUT,FULL−LOAD RFB)

(31)

ΔVOUT,FULL−LOAD is the full−load voltage reduction

from the VID (DAC) setting. ΔVOUT,FULL−LOAD is not the

voltage change from the no−load AVP setting.

7. Current Sensing

For inductive current sensing, choose the current sense

network (RCSx, CCSx, x = 1, 2, 3, or 4) to satisfy

RCSx @ CCSx + Lo (RL ) RPCB)

(32)

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