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EM346-RTR データシート(PDF) 129 Page - Silicon Laboratories

部品番号 EM346-RTR
部品情報  High-Performance, Integrated Dual ZigBee PRO
PDF  142 Pages
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メーカー  SILABS [Silicon Laboratories]
ホームページ  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM346-RTR データシート(HTML) 129 Page - Silicon Laboratories

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EM346
130
Rev 1.0
Figure 18.2. Solder Mask Dimensions
Table 18.2. PCB Land Pattern
Dimension
Min
Max
C1
6.80
6.90
C2
6.80
6.90
E
0.50 BSC
X1
0.20
0.30
X2
5.20
5.40
Y1
0.75
0.85
Y2
5.20
5.40
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60mm minimum, all the way around the pad.
Stencil Design
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2.
The stencil thickness should be 0.125 mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4.
A 4x4 array of 1.1 mm square openings on 1.3 mm pitch can be used for the center ground pad.
Card Assembly
1.
A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.



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