LAN9730 datasheet(21/222 Pages) MICROCHIP

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DS00001946A-page 21

LAN9730/LAN9730i

Ethernet Link

Activity Indi-

cator LED

nLNKA_LED

OD12

(PU)

This pin is driven low (LED on) when a valid link is

detected. This pin is pulsed high (LED off) for

80 ms whenever transmit or receive activity is

detected. This pin is then driven low again for a

minimum of 80 ms, after which time it will repeat

the process if TX or RX activity is detected. Effec-

tively, LED2 is activated solid for a link. When

transmit or receive activity is sensed, LED2 will

function as an activity indicator.

General Pur-

pose I/O 9

GPIO9

IS/O12/

OD12

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

Note:

This pin may serve as the

PME_MODE_SEL input when External

PHY and PME Modes of operation are

in effect. Refer to Chapter 5.0, "PME

Operation" for additional information.

Note:

By default this pin is configured as a

GPIO.

Ethernet

Speed Indica-

tor LED

nSPD_LED

OD12

(PU)

This pin is driven low (LED on) when the Ethernet

operating speed is 100 Mbs, or during auto-nego-

tiation. This pin is driven high during 10 Mbs oper-

ation or during line isolation.

General Pur-

pose I/O 10

GPIO10

IS/O12/

OD12

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

Note:

This pin may serve as a wakeup pin

whose detection mode is selectable

when External PHY and PME Modes of

operation are in effect. Refer to Chapter

5.0, "PME Operation" for additional

information.

Note:

By default this pin is configured as a

GPIO.

Core Regula-

tor Enable

CORE_REG_EN

This pin enables/disables the internal core logic

voltage regulator.

When tied low to VSS, the internal core regulator

is disabled and +1.2 V must be supplied to the

device by an external source.

When tied high to +3.3 V, the internal core regula-

tor is enabled.

Refer to Chapter 3.0, "Power Connections" and

the device reference schematics for connection

information.

Test 1

TEST1

This pin must always be connected to VSS for

proper operation.

TABLE 2-4:

MISCELLANEOUS PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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