USB3370 datasheet(20/75 Pages) MICROCHIP

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USB3370

DS00001915B-page 20

 2012 - 2015 Microchip Technology Inc.

5.5.1.1

ULPI Clock Input Mode (60MHz REFCLK Mode)

When using ULPI Clock Input Mode, the Link must supply the 60MHz ULPI clock to the USB3370. In this mode the

60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDDIO.

After the PLL has locked to the correct frequency, the USB3370 will de-assert DIR and the Link can begin using the

ULPI interface. The USB3370 is ensured to start the clock within the time specified in Table 4-2. For Host applications,

the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4.

For the USB3370, the REF pins should be tied to ground.

5.5.1.2

ULPI Clock Output Mode

When using ULPI Clock Output Mode, the USB3370 generates the 60MHz ULPI clock used by the Link. In this mode,

the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60MHz ULPI clock

to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or hard-

ware reset with a voltage that exceeds the value of VIH_ED provided in Table 4-3. An example of ULPI Clock Output

Mode is shown in Figure 8-1

After the PLL has locked to the correct frequency, the USB3370 generates the 60MHz ULPI clock on the CLKOUT pin,

and de-asserts DIR to indicate that the PLL is locked. The USB3370 is ensured to start the clock within the time specified

in Table 4-2, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be

enabled. This is described in Section 6.4.1.4.

When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI

interface signals. There is no need to align the phase of the REFCLK and the CLKOUT.

FIGURE 5-2:

CONFIGURING THE USB3370 FOR ULPI CLOCK INPUT MODE (60 MHZ)

CLKOUT

REFCLK

PHY

Clock

Source

To PLL

Link

ULPI Clk Out

Reference Clk In

VDD18/

VDDIO

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