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SL11RIDE
Document #: 38-08007 Rev. **
Page 17 of 27
Note: Clock is 48 MHz nominal.
9.6
Reset Circuit
Figure 9-1. Reset Circuit Sample
9.7
SL11RIDE PIO Read/Write Cycle
At power-up and during Read/Write Cycles, the SL11RIDE uses PIO mode 2 timing for the data transfer from/to device. See
chapter 10 in the section 10.2.2 of [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5) for more detail.
10.0
Appendix
This is a pin translation of SL11RIDE signals to 36, 44, 50, and 68 of the Storage Device Class, which is based on the latest AT
Attachment specification and Compact Flash Specification Version 1.4.
These signals connect directly to the ATAPI/IDE devices. If you intend to design for a long IDE cable, then you have to use RC
Termination. See [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5).
10.1
SL11RIDE Pin Translation: 36-Pin–40-Pin Signals
Parameter
Description
Min.
Typical
Max.
VCC
Operating Voltage Range
5.5V
tRPU
Time Reset Pull up
150 ms
Vmax
Voltage reach max
VDD – 0.7V
VRH
Voltage Reset High
3.0V
treset
nRESET Pulse width
16 clocks
tioact
nRESET high to nRD
16 clocks
Table 10-1. 36-pin to 40-pin Interface Signals
SL11RIDE Signal
36-Pin Signal
36-Pin
Translates
40-Pin
GND
GND
1
→
2
nRESET
RESET
2
→
1
D8
D8
3
→
4
D7
D7
4
→
3
D9
D9
5
→
6
D6
D6
6
→
5
D10
D10
7
→
8
6/5,'( Microcontroller
0&
3
5(6(7
9&&
*1'
µ)
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