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SL11RIDE
Document #: 38-08007 Rev. **
Page 26 of 27
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
D15-D4
Reserved
should be set to all zeros.
Note:
Upon reset, the lowest speed is selected for low power operation. The SL11R BIOS will configure the clock to 24 MHz as part of
its initialization.
SPD3-0
SL11R Speed
0000
48.00 MHz.
0001
24.00 MHz.
0010
16.00 MHz.
0011
12.00 MHz.
0100
09.60 MHz.
0101
08.00 MHz.
0110
06.86 MHz.
0111
06.00 MHz.
1000
05.33 MHz.
1001
04.80 MHz.
1010
04.36 MHz.
1011
04.00 MHz.
1100
03.69 MHz.
1101
03.42 MHz.
1110
03.20 MHz.
1111
03.00 MHz.
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