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AD6676EBZ データシート(PDF) 81 Page - Analog Devices

部品番号 AD6676EBZ
部品情報  Wideband IF Receiver Subsystem
PDF  90 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD6676EBZ データシート(HTML) 81 Page - Analog Devices

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Data Sheet
AD6676
Rev. A | Page 81 of 90
JESD204 M Register
Address: 0x1C6, Reset: 0x01, Name: M
Table 96. Bit Descriptions for M
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
M
M.
0x01
RW
00000001
Two converters (I/Q data).
JESD204 S Register
Address: 0x1C9, Reset: 0x00, Name: S
Table 97. Bit Descriptions for S
Bits
Bit Name
Settings
Description
Reset
Access
[7:5]
RESERVED
0x0
RW
[4:0]
S
S.
0x00
RW
00000
One sample per frame (the only valid option).
JESD204 RES1 Register
Address: 0x1CB, Reset: 0x00, Name: RES1
Table 98. Bit Descriptions for RES1
Bits
Bit Name
Description
Reset
Access
[7:0]
RES1
0x00
RW
JESD204 RES2 Register
Address: 0x1CC, Reset: 0x00, Name: RES2
Table 99. Bit Descriptions for RES2
Bits
Bit Name
Description
Reset
Access
[7:0]
RES2
0x00
RW
JESD204 LID0 Register
Address: 0x1D0, Reset: 0x00, Name: LID0
Table 100. Bit Descriptions for LID0
Bits
Bit Name
Description
Reset
Access
[7:5]
RESERVED
0x0
RW
[4:0]
LID0
Lane ID for Lane 0.
0x00
RW
JESD204 LID1 Register
Address: 0x1D1, Reset: 0x01, Name: LID1
Table 101. Bit Descriptions for LID1
Bits
Bit Name
Description
Reset
Access
[7:5]
RESERVED
0x0
RW
[4:0]
LID1
Lane ID for Lane 1.
0x01
RW



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