ADM1270ARQZ-R7 datasheet(20/21 Pages) AD

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ADM1270

Data Sheet

Rev. A | Page 20 of 21

POWER GOOD

The power-good (PWRGD) output can be used to indicate

whether the output voltage exceeds a user defined threshold

and can, therefore, be considered good. The PWRGD output

is set by a resistor divider connected to the FB_PG pin (see

Figure 42).

40×

–

VCC/SENSE+

SENSE–

GATE

GND

LDO

GATE DRIVE/

LOGIC

VCAP

RSENSE

FB_PG

4V TO 60V

–

Figure 42. Generation of PWRGD Signal

When the voltage at the FB_PG pin exceeds the 1 V threshold

(indicating that the output voltage has risen), the open-drain

pull-down current is disabled, allowing PWRGD to be pulled

high. The PWRGD pin is an open-drain output that pulls low

when the voltage at the FB_PG pin is lower than the 1 V

threshold minus the hysteresis (power bad). Hysteresis on the

FB_PG pin is fixed at 30 mV. PWRGD is guaranteed to be in a

valid state for VCC ≥ 1.7 V.

Calculate the power-good threshold using the following

equation:

VPWRGD = 1 V × (1 + RPG1/RPG2)

where:

RPG1 is the resistance from VOUT to FB_PG.

RPG2 is the resistance from FB_PG to GND.

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