COP688CS datasheet(25/53 Pages) NSC

部品番号	COP688CS

部品情報	8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory, Comparators and USART

PDF	53 Pages

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メーカー	NSC [National Semiconductor (TI)]

ホームページ	http://www.national.com

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25 / 53 page

USART (Continued)

USART CONTROL AND STATUS REGISTERS

The operation of the USART is programmed through three

registers: ENU, ENUR and ENUI.

DESCRIPTION OF USART REGISTER BITS

ENU-USART Control and Status Register (Address at 0BA)

PEN

PSEL1

XBIT9/

CHL1

CHL0

ERR

RBFL

TBMT

PSEL0

Bit 7

Bit 0

PEN: This bit enables/disables Parity (7- and 8-bit modes

only). Read/Write, cleared on reset.

PEN = 0

Parity disabled.

PEN = 1

Parity enabled.

PSEL1, PSEL0: Parity select bits. Read/Write, cleared on

reset.

PSEL1 = 0, PSEL0 = 0

Odd Parity (if Parity enabled)

PSEL1 = 0, PSEL0 = 1

Even Parity (if Parity enabled)

PSEL1 = 1, PSEL0 = 0

Mark(1) (if Parity enabled)

PSEL1 = 1, PSEL0 = 1

Space(0) (if Parity enabled)

XBIT9/PSEL0: Programs the ninth bit for transmission when

the USART is operating with nine data bits per frame. For

seven or eight data bits per frame, this bit in conjunction with

PSEL1 selects parity. Read/Write, cleared on reset.

DS012829-14

FIGURE 12. USART Block Diagram

COP688CS データシート(PDF) 25 Page - National Semiconductor (TI)

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