COP688CS datasheet(38/53 Pages) NSC

38 / 53 page

WATCHDOG

The device contains a WATCHDOG and clock monitor. The

WATCHDOG is designed to detect the user program getting

stuck in infinite loops resulting in loss of program control or

“runaway” programs. The Clock Monitor is used to detect the

absence of a clock or a very slow clock below a specified

rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 6 shows the WDSVR register.

TABLE 6. WATCHDOG Service Register (WDSVR)

Window

Key Data

Clock

Select

Monitor

01100

54321

The lower limit of the service window is fixed at 2048 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 7 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

TABLE 7. WATCHDOG Service Window Select

WDSVR

Clock

Service Window

Bit 7

Bit 6

Monitor

(Lower-Upper Limits)

2048–8k t

C Cycles

2048–16k t

C Cycles

2048–32k t

C Cycles

2048–64k t

C Cycles

Clock Monitor Disabled

Clock Monitor Enabled

Clock Monitor

The Clock Monitor aboard the device can be selected or de-

selected under program control. The Clock Monitor is guar-

anteed not to reject the clock if the instruction cycle clock (1/

c) is greater or equal to 10 kHz. This equates to a clock input

rate on CKI of greater or equal to 100 kHz.

WATCHDOG Operation

The WATCHDOG and Clock Monitor are disabled during re-

set. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR reg-

ister involves two irrevocable choices: (i) the selection of the

WATCHDOG service window (ii) enabling or disabling of the

Clock Monitor. Hence, the first write to WDSVR Register in-

volves selecting or deselecting the Clock Monitor, select the

WATCHDOG service window and match the WATCHDOG

key data. Subsequent writes to the WDSVR register will

compare the value being written by the user to the WATCH-

DOG service window value and the key data (bits 7 through

1) in the WDSVR Register.

Table 8 shows the sequence of

events that can occur.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period be-

tween the lower and upper limits of the service window. The

first write to the WDSVR Register is also counted as a

WATCHDOG service.

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low. The WDOUT pin is in the high impedance state in the in-

active state. Upon triggering the WATCHDOG, the logic will

pull the WDOUT (G1) pin low for an additional 16 t

c–32 tc

cycles after the signal level on WDOUT pin goes below the

lower Schmitt trigger threshold. After this delay, the device

will stop forcing the WDOUT output low.

The WATCHDOG service window will restart when the WD-

OUT pin goes high. It is recommended that the user tie the

WDOUT pin back to V

CC through a resistor in order to pull

WDOUT high.

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will enter high impedance state.

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will enter the high imped-

ance TRI-STATE mode following 16 t

c–32 tc clock cycles.

The Clock Monitor generates a continual Clock Monitor error

if the oscillator fails to start, or fails to reach the minimum

specified frequency. The specification for the Clock Monitor

is as follows:

1/t

c > 10 kHz — No clock rejection.

1/t

c < 10 Hz — Guaranteed clock rejection.

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•

Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having he

maximum service window selected.

•

The WATCHDOG service window and CLOCK MONI-

TOR enable/disable option can only be changed once,

during the initial WATCHDOG service following RESET.

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