CPC7692BA datasheet(12/18 Pages) IXYS

12 / 18 page

INTEGRATED CIRCUITS DIVISION

CPC7692

www.ixysic.com

R01

commands to the all off state. Upon restoration of VDD

the switches will remain in the all-off state until the

LATCH input is pulled low.

The rising VDD lock out release threshold is internally

set to ensure all internal logic is properly biased and

functional before accepting external switch commands

from the inputs to control the switch states. For a

falling VDD event, the lock out threshold is set to

assure proper logic and switch behavior up to the

moment the switches are forced off and external

inputs are suppressed.

To facilitate hot plug insertion and power up control the

LATCH pin has an integrated weak pull up resistor to

the VDD power rail that will hold a non-driven LATCH

pin at a logic high state. This enables board designers

to use the CPC7692 with FPGAs and other devices

that provide high impedance outputs during power up

and configuration. The weak pull up allows a fan out of

up to 32 when the system’s LATCH control driver has

a logic low minimum sink capability of 4mA.

2.2.2 Hot Plug and Power Up Circuit Design

Considerations

There are six possible start up scenarios that can

occur during power up. They are:

All inputs defined at power up & LATCH = 0

All inputs defined at power up & LATCH = 1

All inputs defined at power up & LATCH = Z

All inputs not defined at power up & LATCH = 0

All inputs not defined at power up & LATCH = 1

All inputs not defined at power up & LATCH = Z

Under all of the start up situations listed above the

CPC7692 will hold all of it’s switches in the all-off state

during power up. When VDD requirements have been

satisfied the LCAS will complete it’s start up procedure

in one of three conditions.

For start up scenario 1 the CPC7692 will transition

from the all off state to the state defined by the inputs

when VDD is valid.

For start up scenarios 2, 3, 5, and 6 the CPC7692 will

power up in the all-off state and remain there until the

LATCH pin is pulled low. This allows for an indefinite

all off state for boards inserted into a powered system

but are not configured for service or boards that need

to wait for other devices to be configured first.

Start up scenario 4 will start up with all switches in the

all-off state but upon the acceptance of a valid VDD the

LCAS will revert to one of the legitimate states listed in

the truth tables and there after may randomly change

states based on input pin leakage currents and

loading. Because the LCAS state after power up can

not be predicted with this start up condition it should

never be utilized.

On designs that do not wish to individually control the

LATCH pins of multi-port cards it is possible to bus

many (or all) of the LATCH pins together to create a

single board level input enable control.

2.3 Switch Logic

2.3.1 Start-up

The CPC7692 uses smart logic to monitor the VDD

supply. Any time the VDD is below an internally set

threshold, the smart logic places the Switch Control

Logic into the all-off state. An internal pullup at the

LATCH pin locks the CPC7692 in the all-off state

following start-up until the LATCH pin is pulled down to

a logic low. Prior to the assertion of a logic low at the

LATCH pin, the switch control inputs must be properly

conditioned.

2.3.2 Switch Timing

The CPC7692 provides, when switching from the

ringing state to the talk state, the ability to control the

release timing of the ringing switches SW3 and SW4

relative to the state of the switches SW1 and SW2

using simple TTL logic-level inputs. The two available

techniques are referred to as make-before-break and

break-before-make operation. When the break switch

contacts of SW1 and SW2 are closed (made) before

the ringing switch contacts of SW3 and SW4 are

opened (broken), this is referred to as

make-before-break operation. Break-before-make

operation occurs when the ringing contacts of SW3

and SW4 are opened (broken) before the switch

contacts of SW1 and SW2 are closed (made). With

the CPC7692, make-before-break and

break-before-make operations can easily be

accomplished by applying the proper sequence of

logic-level inputs to the device.

The logic sequences for either mode of operation are

provided in “Ringing to Talk Transition Logic

Sequence for All Versions: Make-Before-Break”

on page 13, “Ringing to Talk Transition Logic

CPC7692BA データシート(PDF) 12 Page - IXYS Corporation

CPC7692BA データシート(HTML) 12 Page - IXYS Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

データシートダウンロード