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CPC7692BA データシート(PDF) 14 Page - IXYS Corporation |
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CPC7692BA データシート(HTML) 14 Page - IXYS Corporation |
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14 / 18 page ![]() INTEGRATED CIRCUITS DIVISION CPC7692 14 www.ixysic.com R01 2.3.5 Break-Before-Make Operation - All Versions The second break-before-make method for the CPC7692BA/B is also the only method available for the CPC7692BC. As shown in “CPC7692BA and CPC7692BB Truth Table” on page 10 and “CPC7692BC Truth Table” on page 10, the bidirectional TSD interface disables all of the CPC7692 switches when pulled to a logic low. Although logically disabled, an active (closed) ringing switch (SW4) will remain closed until the next zero crossing current event. As shown in the table “Ringing to Talk Transition Logic Sequence for all Versions: Break-Before-Make” on page 14, this operation is similar to the one shown in “Ringing to Talk Transition Logic Sequence CPC7692BA/B: Break-Before-Make” on page 13, except in the method used to select the all off state, and in when the INRINGING and INTEST inputs are configured for the talk state. 1. Pull TSD to a logic low to end the ringing state. This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep TSD low for at least one-half the duration of the ringing cycle period to allow sufficient time for a zero crossing current event to occur and for the circuit to enter the break-before-make state. 3. During the TSD low period, set the INRINGING and INTEST inputs to the talk state (0, 0). 4. Release TSD, allowing the internal pull-up to activate the break switches. When using TSD as an input, the two recommended states are “0” which overrides the logic input pins and forces an all off state and “Z” which allows normal switch control via the logic input pins. This requires the use of an open-collector or open-drain type buffer. Ringing to Talk Transition Logic Sequence for all Versions: Break-Before-Make 2.4 Data Latch The CPC7692 has an integrated transparent data latch. The latch enable operation is controlled by TTL logic input levels at the LATCH pin. Data input to the latch is via the input pins INRINGING and INTEST while the output of the data latch are internal nodes used for state control. When the LATCH enable control pin is at a logic 0 the data latch is transparent and the input control signals flow directly through the data latch to the state control circuitry. A change in input will be reflected by a change in the switch state. Whenever the LATCH enable control pin is at logic 1, the data latch is active and data is locked. Subsequent changes to the input controls INRINGING and INTEST will not result in a change to the control logic or affect the existing switch state. The switches will remain in the state they were in when the LATCH changes from logic 0 to logic 1 and will not respond to changes in input as long as the LATCH is at logic 1. However, neither the TSD input nor the TSD output control functions are affected by the latch function. Since internal thermal shutdown control and external “All-off” control is not affected by the state of the LATCH enable input, TSD will override state control. State INRINGING INTEST LATCH TSD Timing Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Test Switches Ringing 1 0 0 Z - Off On On Off All-Off 1 0 X0 Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Off Break- Before- Make 0 0 SW4 has opened Off Off Off Off Talk 0 0 0 Z Close Break Switches On Off Off Off |
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