ADS8341_15 datasheet(17/24 Pages) TI1

17 / 24 page

ADS8341

SBAS136D

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8341 circuitry. This is particu-

larly true if the reference voltage is low and/or the conver-

sion rate is high.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connec-

tions, and digital inputs that occur just prior to latching the

output of the analog comparator. Thus, during any single

conversion for an n-bit SAR converter, there are n “win-

dows” in which large external transient voltages can easily

affect the conversion result. Such glitches might originate

from switching power supplies, nearby digital logic, and

high power devices. The degree of error in the digital output

depends on the reference voltage, layout, and the exact

timing of the external event. The error can change if the

external event changes in time with respect to the DCLK

input.

With this in mind, power to the ADS8341 should be clean

and well bypassed. A 0.1

µF ceramic bypass capacitor should

be placed as close to the device as possible. In addition, a

µF to 10µF capacitor and a 5Ω or 10Ω series resistor may

be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1

µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, make sure that it can

drive the bypass capacitor without oscillation (the series

resistor can help in this case). The ADS8341 draws very

little current from the reference on average, but it does place

larger demands on the reference circuitry over short periods

of time (on each rising edge of DCLK during a conversion).

The ADS8341 architecture offers no inherent rejection of

noise or voltage variation in regards to the reference input.

This is of particular concern when the reference input is tied

to the power supply. Any noise and ripple from the supply

will appear directly in the digital results. While high fre-

quency noise can be filtered out as discussed in the previous

paragraph, voltage variation due to line frequency (50Hz or

60Hz) can be difficult to remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections that are too near the grounding point of a

microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power supply

entry point. The ideal layout will include an analog ground

plane dedicated to the converter and associated analog

circuitry.

ADS8341 データシート(PDF) 17 Page - Texas Instruments

ADS8341 データシート(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシートダウンロード