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ADS8341 データシート(PDF) 14 Page - Texas Instruments |
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ADS8341 データシート(HTML) 14 Page - Texas Instruments |
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14 / 24 page  ADS8341 14 SBAS136D SYMBOL DESCRIPTION MIN TYP MAX UNITS tACQ Acquisition Time 900 ns tDS DIN Valid Prior to DCLK Rising 50 ns tDH DIN Hold After DCLK HIGH 10 ns tDO DCLK Falling to DOUT Valid 100 ns tDV CS Falling to DOUT Enabled 70 ns tTR CS Rising to DOUT Disabled 70 ns tCSS CS Falling to First DCLK Rising 50 ns tCSH CS Rising to DCLK Ignored 0 ns tCH DCLK HIGH 150 ns tCL DCLK LOW 150 ns tBD DCLK Falling to BUSY Rising 100 ns tBDV CS Falling to BUSY Enabled 70 ns tBTR CS Rising to BUSY Disabled 70 ns The other method is shown in Figure 5, which uses 32 clock cycles per conversion; the last seven clock cycles simply shift out zeros on the DOUT line. BUSY and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, BUSY will go LOW. Internal Clock Mode In internal clock mode, the ADS8341 generates its own conversion clock internally. This relieves the microproces- sor from having to generate the SAR conversion clock and allows the conversion result to be read back at the processor’s convenience, at any clock rate from 0MHz to 2.0MHz. BUSY goes LOW at the start of conversion and then returns HIGH when the conversion is complete. During the conver- sion, BUSY will remain LOW for a maximum of 8 µs. Also, during the conversion, DCLK should remain LOW to achieve the best noise performance. The conversion result is stored in an internal register; the data may be clocked out of this register any time after the conversion is complete. If CS is LOW when BUSY goes LOW following a conver- sion, the next falling edge of the external serial clock will write out the MSB on the DOUT line. The remaining bits (D14-D0) will be clocked out on each successive clock cycle following the MSB. If CS is HIGH when BUSY goes LOW then the DOUT line will remain in tri-state until CS goes LOW, as shown in Figure 6. CS does not need to remain LOW once a conversion has started. Note that BUSY is not tri-stated when CS goes HIGH in internal clock mode. Data can be shifted in and out of the ADS8341 at clock rates exceeding 2.4MHz, provided that the minimum acquisition time tACQ, is kept above 1.7µs. Digital Timing Figure 4 and Tables VI and VII provide detailed timing for the digital interface of the ADS8341. TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V, TA = –40°C to +85°C, CLOAD = 50pF). t ACQ Acquire Idle Conversion 1 DCLK CS 81 15 DOUT BUSY (MSB) (START) (LSB) A2 S DIN A1 A0 SGL/ DIF PD1 PD0 14 13 12 11 10 9 8 7654321 0 81 8 Idle 18 Zero Filled... t ACQ Acquire Idle Conversion 1 DCLK CS 8 9 10 1112 13 1415 16 17 18 19 20 2122 23 24 2526 27 28 29 30 3132 15 DOUT BUSY (MSB) (START) (LSB) A2 S DIN A1 A0 SGL/ DIF PD1 PD0 14 13 12 11 10 9 8 7654321 0 Zero Filled... FIGURE 5. External Clock Mode 32 Clocks Per Conversion. FIGURE 6. Internal Clock Mode Timing. SYMBOL DESCRIPTION MIN TYP MAX UNITS tACQ Acquisition Time 1.5 µs tDS DIN Valid Prior to DCLK Rising 100 ns tDH DIN Hold After DCLK HIGH 10 ns tDO DCLK Falling to DOUT Valid 200 ns tDV CS Falling to DOUT Enabled 200 ns tTR CS Rising to DOUT Disabled 200 ns tCSS CS Falling to First DCLK Rising 100 ns tCSH CS Rising to DCLK Ignored 0 ns tCH DCLK HIGH 200 ns tCL DCLK LOW 200 ns tBD DCLK Falling to BUSY Rising 200 ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 ns TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V, TA = –40°C to +85°C, CLOAD = 50pF). |
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