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V62/12615-01XE-R データシート(PDF) 31 Page - Texas Instruments |
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V62/12615-01XE-R データシート(HTML) 31 Page - Texas Instruments |
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31 / 92 page  SD+ internal PMD Input Pair T2.23.1 T2.23.2 Fast link pulses T2.22.1 T2.22.3 T2.22.2 T2.22.1 T2.22.5 T2.22.4 clock pulse clock pulse data pulse FLP burst FLP burst DP83848-EP www.ti.com SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013 3.5.22 Auto-Negotiation Fast Link Pulse (FLP) Timing Figure 3-23. Auto-Negotiation Fast Link Pulse (FLP) Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.22.1 Clock, Data Pulse Width 100 ns T2.22.2 Clock Pulse to Clock Pulse Period 125 μs T2.22.3 Clock Pulse to Data Pulse Period Data = 1 62 μs T2.22.4 Burst Width 2 ms T2.22.5 FLP Burst to FLP Burst Period 16 ms 3.5.23 100BASE-TX Signal Detect Timing Figure 3-24. 100BASE-TX Signal Detect Timing xxx PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.23.1 SD Internal Turn-on Time 1 ms T2.23.2 SD Internal Turn-off Time 350 µs (1) The signal amplitude on PMD Input Pair must be TP-PMD compliant. Copyright © 2012–2013, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 31 Submit Documentation Feedback Product Folder Links: DP83848-EP |
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