A1

0402 Decoupling

Cap

MCLK_IN

GND

CLK_REQ2

CLK_REQ1

CLK_OUT2

CLK_OUT1

= Via to GND Plane

= GND Trace

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0

10

20

30

40

50

60

70

80

90

100

Tim e (ns)

MCLK_IN

CLK_OUT1

V

= 3.3 V

C

= 1 µF

C

= 0.1 µF C

= 30 pF

BATT

VLDO

BATT

OUT

CDC3RL02

www.ti.com

SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016

9.2.3 Application Curves

Figure 13. Sine Wave Input vs Output

10 Power Supply Recommendations

General power supply recommendations are to be considered for the CDC3RL02. These include:

•

•

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

•

pin

•

Short trace-lengths should be used to avoid excessive loading

•

For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to

minimize crosstalk and EMI

11.2 Layout Example

Figure 14. Example Layout for YFP Package

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