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SLK2501IPZP データシート(PDF) 8 Page - Texas Instruments |
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SLK2501IPZP データシート(HTML) 8 Page - Texas Instruments |
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8 / 22 page ![]() www.ti.com Clock and Data Recovery Minimum Transition Density Jitter Transfer Jitter Tolerance SLK2501 SLLS502C – OCTOBER 2001 – REVISED MARCH 2007 The CDR unit of the SLK2501 device recovers the clock and data from the incoming data streams. In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency stability. If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the LOL pin is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm. The loop filter transfer function is optimized to enable the CDR to track ppm difference in the clocking and tolerate the minimum transition density that can be received in a SONET data signal ( ±20 ppm). The transfer function yields a typical capture time of 3500-bit times for random incoming NRZ data after the device is powered up and achieves frequency locking. The device tolerates up to 72 consecutive digits (CID) without sustaining an error. The jitter transfer is less than the mask shown in Figure 2 (GR-253 Figure 5-27). Jitter transfer function is defined as the ratio of jitter on the output signal to the jitter applied on the input signal versus frequency. The input sinusoidal jitter amplitude is applied up to the mask level in the jitter tolerance requirement (see Figure 3). Figure 2. Jitter Transfer Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes the equivalent 1-dB optical/electrical power penalty. This refers to the ability of the device to withstand input jitter without causing a recovered data error. The device has a jitter tolerance that exceeds the mask shown in Figure 3 (GR-253 Figure 5-28). This jitter tolerance is specified using a pseudorandom data pattern of 231–1. 8 Submit Documentation Feedback |
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