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FEATURES

DESCRIPTION

SLK2501

SLLS502C – OCTOBER 2001 – REVISED MARCH 2007

OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

Optical Modules

• Fully Integrated SONET/SDH Transceiver to

• Hot Plug Protection

Support Clock/Data Recovery and

• Low Jitter PECL-Compatible Differential Serial

Multiplexer/Demultiplexer Functions

Interface With Programmable De-Emphasis for

• Supports OC-48, OC-24, OC-12, Gigabit

the Serial Output

Ethernet, and OC-3 Data Rate With Autorate

• On-Chip Termination for LVDS and

Detection

PECL-Compatible Interface

• Supports Transmit Only, Receiver Only,

• Receiver Differential Input Thresholds 150 mV

Transceiver and Repeater Functions in a

Minimum

Single Chip Through Configuration Pins

• Supports SONET Loop Timing

• Supports SONET/SDH Frame Detection

• Low Power <900 mW at OC-48 Data Rate

• On-Chip PRBS Generation and Verification

• ESD Protection >2 kV

• Supports 4-Bit LVDS (OIF99.102) Electrical

• 622-MHz Reference Clock

Interface

• Maintains Clock Output in Absence of Data

• Parity Checking and Generation for the LVDS

• Local and Remote Loopback

Interface

• 100-Pin PZP Package With PowerPAD™

• Single 2.5-V Power Supply

Design

• Interfaces to Back Plane, Copper Cables, or

The SLK2501 is a single chip, multirate transceiver that derives high-speed timing signals for SONET/

SDH-based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial

conversion, and a frame detection function conforming to the SONET/SDH standards.

The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rates through the rate

selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is

required for the recovery loop, and it also provides a stable clock source in the absence of serial data

transitions.

The SLK2501 accepts 4 bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at

OC-3, OC-12, OC-24 or OC-48 rates. It also recovers the data and clock from the serial SONET stream and

demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits

that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible

differential interface.

The SLK2501 provides a comprehensive suite of built-in tests for self-test purposes including local and remote

AVAILABLE OPTIONS

PowerPAD QUAD (PZP)

–40

°C to 85°C

SLK2501IPZP

(1)

For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI Web site at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2001–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.