LM3203

2.7V to 5.5V

0.8V to 3.6V

L1

3.3 PH

C1*

10 PF

C5*

0.1 PF

C2

4.7 PF

SW

FB

PGND

SGND

10 pF

267k

BYPOUT

R1

R2

133k

C3

BYP

EN

SYSTEM

CONTROLLER

DAC = 0.267V-1.2V

ON/OFF

LM3203

SNVS355D – MAY 2005 – REVISED APRIL 2013

www.ti.com

Figure 31. Typical Operating System Circuit where baseband controls the output voltage using a DAC

Circuit Operation

Referring to Figure 31, the LM3203 operates as follows. During the first part of each switching cycle, the control

block in the LM3203 turns on the internal PFET (P-channel MOSFET) switch. This allows current to flow from the

input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a

controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel

MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage

that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the

stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope

when inductor current is going low, smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the

load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and

synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output

voltage is equal to the average voltage at the SW pin.

PWM Mode

While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant

frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by

modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing

the PFET drain current to a slope-compensated reference current generated by the error amplifier. At the

beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the

current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and

turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output

down, the error amplifier output increases, which allows the inductor current to ramp higher before the

comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase

in the load. The minimum on-time of PFET in PWM mode is 50ns (typ.).

Bypass Mode

The LM3203 contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass mode. In

Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output power.

Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the resistance of the

bypass PFET is less than the series resistance of the PWM PFET and inductor. This translates into higher

voltage available on the output in Bypass mode, for a given battery voltage. The part can be placed in bypass

mode by sending BYP pin high. It remains in bypass mode until BYP pin goes low.

It is recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the

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