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LM3203 データシート(PDF) 13 Page - Texas Instruments

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部品番号 LM3203
部品情報  Step-Down DC-DC Converter
PDF  22 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LM3203 データシート(HTML) 13 Page - Texas Instruments

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LM3203
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SNVS355D – MAY 2005 – REVISED APRIL 2013
Operating Mode Selection Control
The LM3203 is designed for digital control of the operating modes using the BYP pin. Setting the BYP pin high
(>1.2V) places the device in Bypass mode. Setting BYP pin low (<0.4V) forces operation in PWM mode.
Bypass and PWM operation overlap during the transition between the two modes. This transition time is
approximately 31µs when changing from PWM to Bypass mode, and 15µs when changing from Bypass to PWM
mode. This helps prevent under or overshoots during the transition period between PWM and Bypass modes.
Shutdown Mode
Setting the EN digital pin low (<0.4V) places the LM3203 in a 0.1µA (typ.) Shutdown mode. During shutdown, the
PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of the LM3203 are
turned off. Setting EN high (>1.2V) enables normal operation.
EN should be set low to turn off the LM3203 during power-up and under voltage conditions when the power
supply is less than the 2.7V minimum operating voltage. The LM3203 is designed for compact portable
applications, such as mobile phones. In such applications, the system controller determines power supply
sequencing and requirements for small package size outweigh the benefit of including UVLO (Under Voltage
Lock-Out) circuitry.
Dynamically Adjustable Output Voltage
The LM3203 features dynamically adjustable output voltage. The output can be set by changing the voltage on
the analog VCON pin. This feature is useful in PA applications where peak power is needed only when the
handset is far away from the base station or when data is being transmitted. In other instances, the transmitting
power can be reduced. Hence the supply voltage to the PA can be reduced, promoting longer battery life. See
Setting the Output Voltage section for further details.
Over Voltage Protection
The LM3203 has an over voltage comparator that prevents the output voltage from rising too high, when the
device is left in PWM mode under light-load conditions, during output voltage steps, or during startup. When the
FB pin voltage rises by 100mV over the VCON voltage, the OVP comparator inhibits PWM operation to skip
pulses until the feedback voltage returns to the VCON voltage. During the over voltage protection mode, both the
PWM PFET and the NFET synchronous rectifier are off. When the part comes out of the over-voltage protection
mode, the NFET synchronous rectifier remains off for approximately 3.5µs to avoid inductor current going
negative.
Internal Synchronous Rectification
While in PWM mode, the LM3203 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
With medium and heavy loads, the internal NFET synchronous rectifier is turned on during the inductor current
down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. There
is no zero cross detect, which means that the NFET can conduct current in both directions and inductor current is
always continuous. The advantage of this method is that the part remains in PWM mode at light loads or no load
conditions. The NFET has a current limit. The NFET is designed to conduct through its intrinsic body diode
during transient intervals before it turns on, eliminating the need for an external diode.
Current Limiting
A current limit feature allows the LM3203 to protect itself and external components during overload conditions. In
PWM mode, a 940mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output
voltage down to below approximately 0.375V, indicating a possible short to ground, then the device switches to a
timed current limit mode. In timed current limit mode, the internal PFET switch is turned off after the current
comparator trips, and the beginning of the next cycle is inhibited for 3.5µs to force the instantaneous inductor
current to ramp down to a safe value. After the 3.5µs interval, the internal PFET is turned on again. This cycle is
Copyright © 2005–2013, Texas Instruments Incorporated
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