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LP8725TLE-A/NOPB データシート(PDF) 9 Page - Texas Instruments

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部品番号 LP8725TLE-A/NOPB
部品情報  LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems
PDF  46 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LP8725TLE-A/NOPB データシート(HTML) 9 Page - Texas Instruments

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PWR_ON
Buck 1
0 1 2 3
Buck 2
tON
tS
Timing Code
Timing Code
START UP sequence
SHUT DOWN sequence
is in reverse order of START UP sequence
Buck 1
0
1
2
3
Buck 2
LDO1
LDO1
LDO3
LDO3
START UP
tS
tS
tS
tS
tS
tS
tS
tS
tS
tS
tS
SHUT DOWN
IDLE
Note 4
LDO4
LDO4
LDO5
LDO5
LILO 2
LILO 2
LILO 1
LILO 1
4 5 6
6 5 4
LDO2
LDO2
PWR_ON
PS_HOLD
PS_HOLD
tOFF
LP8725
www.ti.com
SNVS618G – DECEMBER 2009 – REVISED MAY 2013
Figure 5. LP8725 Startup and Shutdown Sequence if CONFIG=VIN1 Note 1, Note 2
All timing is typical.
tON/OFF 30 ms typ. de-bounce times
tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy.
Note 1 STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the
registers are not rewritten via Serial Interface.
Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling
process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup
duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications.
Note 4 At this time point registers are reset to POR default values.
Copyright © 2009–2013, Texas Instruments Incorporated
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