P89LPC901FD datasheet(27/55 Pages) PHILIPS

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Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 — 21 November 2003

27 of 55

9397 750 12293

8.6 CPU CLock (CCLK) wake-up delay

The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100

µs.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC901 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK

is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power

consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC901/902/903 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.

8.10 Data RAM arrangement

The 128 bytes of on-chip RAM is organized as follows:

8.11 Interrupts

The P89LPC901/902/903 uses a four priority level interrupt structure. This allows

great ﬂexibility in controlling the handling of the many interrupt sources.

Table 10:

On-chip data memory usages

Type

Data RAM

Size (Bytes)

DATA

Memory that can be addressed directly and indirectly 128

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