P89LPC901FD datasheet(36/55 Pages) PHILIPS

36 / 55 page

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 — 21 November 2003

36 of 55

9397 750 12293

8.18.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit

(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.

The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or

the Baud Rate Generator (described in section Section 8.18.5 “Baud rate generator

and selection”).

8.18.5

Baud rate generator and selection

The P89LPC903 enhanced UART has an independent Baud Rate Generator. The

baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar

manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other

timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 18).

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses CCLK.

8.18.6

Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If

SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)

are set up when SMOD0 is ‘0’.

8.18.7

Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device.

8.18.8

Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ﬁrst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = ‘0’).

Fig 18. Baud rate sources for UART (Modes 1, 3).

Baud Rate Modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

¸2

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

002aaa419

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