HCS500T-ISLASHST datasheet(9/42 Pages) MICROCHIP

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DS40000153E-page 9

HCS500

4.0

INTERFACING TO A

MICROCONTROLLER

The HCS500 interfaces to a microcontroller via a

synchronous serial interface. A clock and data line are

used

communicate

with

the

HCS500.

The

microcontroller controls the clock line. There are two

groups of data transfer messages. The first is from the

decoder whenever the decoder receives a valid

transmission. The decoder signals reception of a valid

code by taking the data line high (maximum of 500 ms)

The microcontroller then services the request by

clocking out a data string from the decoder. The data

string contains the function code, the Status bit, and

block indicators. The second is from the controlling

microcontroller to the decoder in the form of a defined

command set.

Figure 4-1 shows the HCS500 decoder and the I/O

interface

lines

necessary

interface

microcontroller.

4.1

Valid Transmission Message

The decoder informs the microcontroller of a valid

transmission by taking the data line high for up to

500 ms.

The

controlling

microcontroller

must

acknowledge by taking the clock line high. The decoder

then takes the data line low. The microcontroller can

then begin clocking a data stream out of the HCS500.

The data stream consists of:

• Start bit ‘0’.

• Two Status bits [REPEAT, VLOW].

• 4-bit function code [S3 S2 S1 S0].

• Stop bit ‘1’.

• Four bits indicating which block was used

[TX3…TX0].

• Four bits indicating the number of transmitters

learned into the decoder [CNT3…CNT0].

• 64 bits of the received transmission with the

hopping code decrypted.

The decoder will terminate the transmission of the data

stream at any point where the clock is kept low for

longer than 1 ms. Therefore, the microcontroller can

only clock out the required bits. A maximum of 80 bits

can be clocked out of the decoder.

FIGURE 4-1:

HCS500 DECODER AND I/O INTERFACE LINES

Note:

Data is always clocked in/out Least

Significant Bit (LSb) first.

Vss

24LC02

Vcc

SCL

VDD

EE_CLK

EE_DAT

MCLR

Vss

RFIN

S_CLK

S_DAT

VDD

RF RECEIVER

SYNC CLOCK

SYNC DATA

MICRO RESET

HCS500

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