SI5341_16 datasheet(28/53 Pages) SILABS

部品番号	SI5341

部品情報	Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

PDF	53 Pages

Scroll/Zoom	100%

メーカー	SILABS [Silicon Laboratories]

ホームページ	http://www.silabs.com

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Table 5.9. I2C Timing Specifications (SCL,SDA)

Parameter

Symbol

Test Condition

Standard Mode

100 kbps

Fast Mode

400 kbps

Units

Min

Max

Min

Max

SCL Clock Frequency

fSCL

—

100

—

400

kHz

Hold Time (Repeated)

START Condition

tHD:STA

4.0

—

0.6

—

μs

Low Period of the SCL Clock

tLOW

4.7

—

1.3

—

μs

HIGH Period of the SCL

Clock

tHIGH

4.0

—

0.6

—

μs

Set-up Time for a Repeated

START Condition

tSU:STA

4.7

—

0.6

—

μs

Data Hold Time

tHD:DAT

100

—

100

—

Data Set-up Time

tSU:DAT

250

—

100

—

Rise Time of Both SDA and

SCL Signals

—

1000

300

Fall Time of Both SDA and

SCL Signals

—

300

—

300

Set-up Time for STOP Con-

dition

tSU:STO

4.0

—

0.6

—

μs

Bus Free Time between a

STOP and START Condition

tBUF

4.7

—

1.3

—

μs

Data Valid Time

tVD:DAT

—

3.45

—

0.9

μs

Data Valid Acknowledge

Time

tVD:ACK

—

3.45

—

0.9

μs

Si5341/40 Rev D Data Sheet

Electrical Specifications

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