STV9118 datasheet(27/46 Pages) STMICROELECTRONICS

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STV9118

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sults in the change of horizontal position of the pic-

ture. The loop, by tuning the VCO accordingly,

gets and maintains in coincidence the rising edge

of input sync. signal with signal REF1, which is de-

rived from the VCO ramp by a comparator with

threshold adjustable through

HPOS I2C bus con-

trol. The coincidence is identified and flagged by

lock detection circuit on pin HLckVBk as well as by

HLock I2C bus flag.

The charge pump provides positive and negative

currents charging the external loop filter on HPosF

pin. The loop is independent of the trailing edge of

sync. signal and only locks to its leading edge. By

design, the PLL1 does not suffer from any dead

band even while locked. The speed of the PLL1

depends on the current value provided by the

charge pump. While not locked, the current is very

low, to slow down the changes of VCO frequency

and thus protect the external power components

at sync. signal change. In locked state, the cur-

rents are much higher, two different values being

selectable via PLL1Pump I2C bus bit to provide a

mean to control the PLL1 speed by S/W. Lower

values make the PLL1 slower, but more stable.

Higher values make it faster and less stable. In

general, the PLL1 speed should be higher for high

deflection frequencies. The response speed and

stability (jitter level) depends on the choice of ex-

ternal components making up the loop filter. A

“CRC” filter is generally used (see Figure 4 on

page 27).

Figure 4. H-PLL1 filter configuration

The PLL1 is internally inhibited during extracted

vertical sync. pulse (if any) to avoid taking into ac-

count missing or wrong pulses on the phase com-

parator. Inhibition is obtained by forcing the charge

pump output to high impedance state. The inhibi-

tion

mechanism

can

disabled

through

PLL1Pump I2C bus bit.

The Figure 7, in its upper part, shows the position

of the VCO ramp signal in relation to input sync.

pulse for three different positions of adjustment of

horizontal position control

HPOS.

Figure 5. Horizontal PLL1 block diagram

HPLL1F

Lock

Status

PLL

INHIBITION

HPosF

SHAPER

Low

High

LOCK

COMP

CHARGE

PUMP

HPLL1F R0

VCO

HOSC

(I2C)

HPOS

INPUT

INTERFACE

H/HVSyn

Sync

PLL1Pump

V-sync (extracted)

PLL1InhEn

(I2C)

HOscF

DETECTOR

Polarity

V-sync

Extracted

REF1

(pin & I2C)

(I2C)

PLL1

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