PESDXUSB3S_SER

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3 — 26 April 2016

8 of 19

NXP Semiconductors

PESDxUSB3S series

ESD protection for differential data lines

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Transmission Line Pulse (TLP) = 100 ns

Transmission Line Pulse (TLP) = 100 ns

Fig 8.

Dynamic resistance with positive clamping;

typical values

Fig 9.

Dynamic resistance with negative clamping;

typical values

Transmission Line Pulse (TLP) = 5 ns

Transmission Line Pulse (TLP) = 5 ns

Fig 10. Dynamic resistance with positive clamping;

typical values

Fig 11. Dynamic resistance with negative clamping;

typical values

025

20

10

15

5

aaa-021326

10

15

5

20

25

I

(A)

0

-25

0

-5

-15

-10

-20

aaa-021327

-15

-10

-20

-5

0

I

(A)

-25

025

20

10

15

5

aaa-021328

10

15

5

20

25

I

(A)

0

-25

0

-5

-15

-10

-20

aaa-021329

-15

-10

-20

-5

0

I

(A)

-25