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MMPF0200F0AEP データシート(PDF) 7 Page - NXP Semiconductors

部品番号 MMPF0200F0AEP
部品情報  12 channel configurable power management integrated circuit
PDF  114 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0200F0AEP データシート(HTML) 7 Page - NXP Semiconductors

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NXP Semiconductors
7
PF0200
PIN CONNECTIONS
28
VGEN4
O
3.6 V
Analog
VGEN4 regulator output, Bypass with a 4.7
μF ceramic output capacitor.
29
VHALF
I
3.6 V
Analog
Half supply reference for VREFDDR
30
VINREFDDR
I
3.6 V
Analog
VREFDDR regulator input. Bypass with at least 1.0
μF decoupling capacitor as close
to the pin as possible.
31
VREFDDR
O
3.6 V
Analog
VREFDDR regulator output
32
SW3VSSSNS
GND
-
GND
Ground reference for the SW3 regulator. Connect to GNDREF externally via the
board ground plane.
33
SW3BFB (4)
I
3.6 V
Analog
Output voltage feedback for SW3B. Route this trace separately from the high-current
path and terminate at the output capacitance.
34
SW3BIN (4)
I
4.8 V
Analog
Input to SW3B regulator. Bypass with at least a 4.7
μF ceramic capacitor and a
0.1
μF decoupling capacitor as close to the pin as possible.
35
SW3BLX (4)
O
4.8 V
Analog
Regulator 3B switch node connection
36
SW3ALX (4)
O
4.8 V
Analog
Regulator 3A switch node connection
37
SW3AIN (4)
I
4.8 V
Analog
Input to SW3A regulator. Bypass with at least a 4.7
μF ceramic capacitor and a
0.1
μF decoupling capacitor as close to the pin as possible.
38
SW3AFB (4)
I
3.6 V
Analog
Output voltage feedback for SW3A. Route this trace separately from the high-current
path and terminate at the output capacitance.
39
VGEN5
O
3.6 V
Analog
VGEN5 regulator output. Bypass with a 2.2
μF ceramic output capacitor.
40
VIN3
I
4.8 V
Analog
VGEN5, 6 input. Bypass with a 1.0
μF decoupling capacitor as close to the pin as
possible.
41
VGEN6
O
3.6 V
Analog
VGEN6 regulator output. By pass with a 2.2
μF ceramic output capacitor.
42
LICELL
I/O
3.6 V
Analog
Coin cell supply input/output
43
VSNVS
O
3.6 V
Analog
LDO or coin cell output to processor
44
SWBSTFB (4)
I
5.5 V
Analog
Boost regulator feedback. Connect this pin to the output rail close to the load. Keep
this trace away from other noisy traces and planes.
45
SWBSTIN (4)
I
4.8 V
Analog
Input to SWBST regulator. Bypass with at least a 2.2
μF ceramic capacitor and a
0.1
μF decoupling capacitor as close to the pin as possible.
46
SWBSTLX (4)
O
7.5 V
Analog
SWBST switch node connection
47
VDDOTP
I
10 V (3)
Digital &
Analog
Supply to program OTP fuses
48
GNDREF
GND
-
GND
Ground reference for the main band gap regulator.
49
VCORE
O
3.6 V
Analog
Analog Core supply
50
VIN
I
4.8 V
Analog
Main chip supply
51
VCOREDIG
O
1.5 V
Analog
Digital Core supply
52
VCOREREF
O
1.5 V
Analog
Main band gap reference
53
SDA
I/O
3.6 V
Digital
I2C data line (Open drain)
54
SCL
I
3.6 V
Digital
I2C clock
55
VDDIO
I
3.6 V
Analog
Supply for I2C bus. Bypass with 0.1
μF decoupling capacitor as close to the pin as
possible.
56
PWRON
I
3.6 V
Digital
Power On/off from processor
Table 2. PF0200 pin definitions (continued)
Pin
number
Pin name
Pin
function
Max rating
Type
Definition



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