Data Sheet

10

Rev 1.0, 2012-10-01

TLE 8088 EM

Voltage Regulator

Figure 4

Reset Function and Timing Diagram

5.3

Watchdog Operation

After power on, the reset output signal at the NRO pin is kept LOW for the power-on reset delay time

T

15ms. With the LOW to HIGH transition of the signal at NRO the micro controller reset is released.

The TLE8088EM integrates a watchdog function. If WDE is connected to low, the watchdog function is disabled.

If the WDE is connected to 5V or left open, the watchdog function is enabled. A pull up current source is integrated

in the WDE pin.

After the activation of the watchdog function, the timing of the signal on WDI from the micro-controller must

correspond the WD-Period

T

with a HIGH-to-LOW transition at the WDI-pin within the time

T

A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger. To avoid wrong triggering

due to parasitic glitches two HIGH samples followed by two LOW samples (sample period

t

decoded as a valid trigger, see Figure 6. A reset is generated (NRO goes LOW) for the time

T

trigger pulse during the Watchdog Period as shown in Figure 5.

t

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